LM3000 Instruction Set
From BenningtonWiki
All addresses and operands are 8 bits wide. Instructions are 16 bits wide. Every instruction takes two cycles.
Registers
R0 R1 R2 - General purpose registers. 8 bits wide.
A B - ALU registers. 8 bits wide.
PC - Program Counter. 8 bits wide.
SR - Status register. 1 bit Z flag.
Move Register
MOV Rd, Rs ; Rd = Rs
MOV Rd, # ; Rd = #
Move to ALU
MOV a, Rs ; a = Rs
MOV a, # ; a = #
a=A or B
Arithmetic
ADD Rd ; Rd = A + B; Z updated
SUB Rd ; Rd = A - B; Z updated
CMP ; A - B; Z updated
Branch
BRA addr ; unconditional
BNE addr ; if Z = 0
BEQ addr ; if Z = 1
d=0-2, s=0-2, addr=0-255, #=0-255 (-128-+127)
Instruction Instruction Code Operand Example
7 6 5 4 3 2 1 0
MOV Rd, Rs 0 0 0 0 d d s s 0 0100 MOV R0, R1
MOV Rd, # 0 0 0 1 d d 1 1 # 130A MOV R0, #10
MOV a, Rs 0 0 1 0 0 a s s 0 2000 MOV A, R0
MOV a, # 0 0 1 1 0 a 1 1 # 330A MOV A, #10
ADD Rd 0 1 0 0 d d 0 0 0 4000 ADD R0
SUB Rd 0 1 0 0 d d 0 1 0 4100 SUB R0
CMP 0 1 0 0 1 1 0 1 0 4D00 CMP
BRA addr 1 1 1 1 0 0 0 0 addr F02A BRA 42
BNE addr 1 1 1 1 1 0 0 0 addr F82A BNE 42
BEQ addr 1 1 1 1 1 1 0 0 addr FC2A BEQ 42
Notes:
Bits 5-7 indicate the instruction type:
000 Move Register
001 Move to ALU
010 Arithmetic
111 Branch
Bit 4 indicates whether the instruction operand should be put on the data bus.
The meaning of bits 0-3 depend on the instruction type:
ddss Move Register: destination register, source register.
0ass Move to ALU: A or B destination, source register.
dd0x ALU: destination register, operation (0=add, 1=sub).
zv00 Branch: Look at the Z flag (0=no, 1=yes), value necessary for branch.
Some common operations
; ADD R0, #1
00 2000 MOV A, R0 ; R0 = R0 + 1
01 3701 MOV B, #1
02 4000 ADD R0
; NOP
00 0000 MOV R0, R0 ; No flags affected
; NEG R0
00 3300 MOV A, #0 ; R0 = 0 - R0
01 2400 MOV B, R0
02 4100 SUB R0
Math operations are performed in three steps:
- Load the first operand into the ALU.
- Load the second operand into the ALU.
- Perform the operation (indicating the destination register).
