The instruction decoder is basically a really big de-multiplexer, and to me, is the part that really shows Joe's mystery area of hardware meeting software.

A pre-requisite to building the instruction decoder, like any other decoding process, is to have the instructions and code first. Luckily, Joe designed that in a logical, 1 byte manner. (See Joe's instructions. There's an explanation of the logic on there also.)

There are four main parts to the code

• Move between registers
• Move to ALU
• Arithmetic functions (see Eben's Unit) Add, Subtract, compare
• Branches

To take a short digression, all the inputs and outputs of all the chips are hooked up to the Data Bus. The data bus is the term for the set of wires that connects all of the chips with an input and output. Basically, that would include the Operand RAM, the registers, the program counter, the status register and the ALU. The data bus is there to enable communication between all these parts, because at some instruction, each of those parts will need to communicate to the other parts, so it's more convenient to have them all on one line. But we don't always want every chip to be writing to the data bus, or to be receiving from the data bus. That would lose the point of having memory on those chips. So the instruction decoder determines the input enable and the output enable of each chip. (The pattern was earlier determined by the instruction code, and to have a manageable code, each instruction only involves two components at a time.)

Joe organized the instruction decoder schematic into an organized, right angle-based drawing which he will post later. The instruction decoder is really just a bunch of combinatorial logic transforming the software into hardware.

-- ReidGinoza - 17 Dec 2005