Bringing Up 6502
I want us to create a howto for the 6502, so that others with a similar interest in old microprocessors can bring up a 6502 the way we did. I'd like to include schematics, parts lists, ideas, stories, pictures.
- Use 32K SRAM, $5 - Jameco #41970PS, datasheet
- Use 2K EEPROM, $4 - Jameco #74691PS, datasheet
- Use a 74154 to do address decoding. Duh. Notice how it's used on the Robotron ROM Board. datasheet
I didn't know EEPROMs are so easy to program. The last time I used Programmable ROMs was at Adobe fifteen years ago and we used ultraviolet boxes to erase the ROMs and custom (I'm assuming expensive) hardware to program them. It was a long and tedious process, getting the ROM data files into the custom hardware (I think it was via serial, or floppy?), then setting up the programmer for the particular brand and type of ROM (I remember a mess of little on-screen menus), then a long wait while the programmer did its work. Erasing the ROMs meant sliding them on a little tray into the ultraviolet box and blasting them for 20 minutes. Don't look into the light!
The double-Es in EEPROM stand for electrically erasable. But that doesn't convey just how cool and easy to program EEPROMs are. The EEPROM has three control lines: Chip Enable (CE), Output Enable (OE) and Write Enable (WE). All of these are active low. Reading data from the ROM is identical to reading data from RAM: place the address on the address lines, enable CE, then enable OE and read the byte on the data lines (CE has to be enabled for 200ns and OE for at least 80ns before reading the data). The real magic happens when you want to program the ROM. It's almost as simple as writing to static RAM. Put the address on the address lines, the byte on the data lines, enable CE, then enable WE for at least 150ns. That's it. The byte is written into the ROM. It takes at most 10ms for the write to complete. To write additional bytes you can just spin for 10ms, but there's a cool little trick for determining when the write is actually finished. 15ns after disabling WE you can start reading data bit 7 at the address written. While the write is in progress it will be the complement of the actual value of the bit just written. As soon as the write is complete it will output the true value of the bit.
6502s don't like to be clocked slowly. We thought we could single cycle the CPU by simply feeding it one-shots from a push button connected to Clock 0. No. After a second or more between clocks the CPU starts wigging out and pulsing strange things on the address and data lines. It occurs to me that the CPU needs a steady clock in order to maintain internal state in addition to advancing internal state. Perhaps the bits inside are dynamic and need refreshing, like dynamic RAM. With a 555 oscillator driving the CPU it seemed to work fine at 40Hz. Even at about 2Hz it worked nearly okay, but the program counter seemed to lose its 12th bit occasionally (odd), clearing it when it should have stayed set.
VCC means power; VSS means ground. ...
- Let's put links to the various PDFs here.
- Programming Model included the Start-up Diagram (9-4)
- was it the hardware manual that had the single-cycle testing?
- Let's mention the books we used.
- Looked at Apple II schematics.
We have a static RAM in the lower bits. This RAM, 43256, is 32k bits, which means it uses up the first 15 lines of address space (out of sixteen) and half of the address space. This means it receives the A0-A14 into its A0-A14. The A15 line from the 6502 goes into the Chip Enable of the RAM. To reiterate, the 43256 responds to addresses all the way from 0000 till 7FFF.
The EEPROM,2816, sits up high on the address space. This is 2k. It has 11 (A0-A10) address lines and will sit at the top from F000 to FFFF. We're just using the upper four bits, so there will be a "Ghost ROM" from F000 to EFFF.
If we use the upper two bits, we can set aside from E000 to EFFF. (Send A14 through a NOT and send that output to an AND with A15.) That we can use for our keyboard.